Isolation techniques for reducing dark current in CMOS image sensors

ABSTRACT

A structure for isolating areas in a semiconductor device is provided. The structure includes a trench having first and second portions formed in a substrate. The first portion has a first width, and the second portion has a second width and is below the first portion. The first width is greater than the second width. A first insulating liner is formed along at least lateral sidewalls of the first portion. A spacer material is formed along at least lateral sidewalls of the insulating liner and filling the second portion. A filler material is over said spacer material and within the first portion. Methods for forming the structure are also provided.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation-in-part of U.S. application Ser. No. 10/291,772, filed on Nov. 12, 2002, now U.S. Pat. No. 6,888,214, issued May 3, 2005, the disclosure of which is herewith incorporated by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor devices, and more particularly, to trench isolation technology for use in semiconductor devices, including CMOS image sensors.

BACKGROUND OF THE INVENTION

In silicon integrated circuit (IC) fabrication, it is often necessary to isolate semiconductor devices formed in the substrate. This is true for many semiconductor memory devices, for example, DRAM, flash memory, SRAM, microprocessors, DSP and ASIC. The individual pixels of a CMOS image sensor also need to be isolated from each other.

A CMOS image sensor circuit includes a focal plane array of pixel cells, each one of the cells includes a photogate, photoconductor, or photodiode overlying a charge accumulation region within a substrate for accumulating photo-generated charge. Each pixel cell may include a transistor for transferring charge from the charge accumulation region to a floating diffusion node and a transistor, for resetting the diffusion node to a predetermined charge level prior to charge transference. The pixel cell may also include a source follower transistor for receiving and amplifying charge from the diffusion node and an access transistor for controlling the readout of the cell contents from the source follower transistor.

In a CMOS image sensor, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge from the floating diffusion node. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS image sensor pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate. A photon impinging on a particular pixel of a photosensitive device may diffuse to an adjacent pixel, resulting in detection of the photon by the wrong pixel, i.e. cross-talk. Therefore, CMOS image sensor pixels must be isolated from one another to avoid pixel cross talk. In the case of CMOS image sensors, which are intentionally fabricated to be sensitive to light, it is advantageous to provide both electrical and optical isolation between pixels.

CMOS image sensors of the type discussed above are generally known as discussed, for example, in Nixon et al., “256.times.256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994). See also U.S. Pat. Nos. 6,177,333 and 6,204,524, which describe operation of conventional CMOS image sensors, the contents of which are incorporated herein by reference.

Shallow trench isolation (STI) is one technique, which can be used to isolate pixels, devices or circuitry from one another. In general, a trench is etched into the substrate and filled with a dielectric to provide a physical and electrical barrier between adjacent pixels, devices, or circuitry. Refilled trench structures, for example, are formed by etching a trench by a dry anisotropic or other etching process and then filling it with a dielectric such as a chemical vapor deposited (CVD) silicon dioxide (SiO₂). The filled trench is then planarized by an etch-back process so that the dielectric remains only in the trench and its top surface remains level with that of the silicon substrate. The depth of a shallow trench is generally from about 2000 to about 2500 Angstroms.

One drawback associated with shallow trench isolation in the case of CMOS image sensors is cross-talk from a photon impinging on a particular pixel of a photosensitive device causing changes that may diffuse under the shallow trench isolation structure to an adjacent pixel. Another drawback is that a hole accumulation layer along the sidewall of the trench is relatively small since it is limited by the depth of the shallow trenches.

One technique which may be used to improve pixel isolation in CMOS image sensors is to implant dopants beneath the isolation region; however, it has been found that this may contribute undesirably to pixel dark current. Minimizing dark current in the photodiode is a key device optimization step in CMOS image sensor fabrication.

It is desirable to provide an isolation technique that prevents cross-talk between pixels while reducing dark current or current leakage as much as possible. It is also desirable to provide an isolation technique while increasing a hole accumulation region adjacent a pixel isolation region.

BRIEF SUMMARY OF THE INVENTION

In one aspect, the invention provides a structure for isolating areas in a semiconductor device having a trench filled with a conductive material containing silicon formed in an active layer of a substrate to isolate adjacent regions. The conductive material containing silicon may be doped with n-type or p-type dopants prior to or after deposition of the material. Preferred conductive materials containing silicon include polysilicon and silicon-germanium. In another aspect, the invention provides forming a trench adjacent an active layer of a substrate, growing an epitaxial layer to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.

In another aspect of the invention, a structure for isolating areas in a semiconductor device includes a trench having first and second portions formed in a substrate. The first portion has a first width, and the second portion has a second width and is below the first portion. The first width is greater than the second width. A first insulating liner is formed along at least lateral sidewalls of the first portion. A spacer material is formed along at least lateral sidewalls of the insulating liner and filling the second portion. A filler material is over said spacer material and within the first portion. Methods for forming the structure are also provided.

These and other features and advantages of the invention will be more apparent from the following detailed description that is provided in connection with the accompanying drawings and illustrate exemplary embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top plan view of an exemplary CMOS image sensor fragment;

FIG. 1B is a diagrammatic side sectional view of the FIG. 1A image sensor fragment taken along line 1B-1B;

FIG. 2 is a diagrammatic side sectional view of a CMOS image sensor fragment at an initial stage of processing and in accordance with an exemplary embodiment of the invention;

FIGS. 3-5 illustrate the CMOS image sensor of FIG. 2 at intermediate steps of processing;

FIG. 6 is a diagrammatic side sectional view of a CMOS image sensor fragment resulting from the processes depicted in FIGS. 2-5;

FIG. 7 is a diagrammatic side sectional view of a CMOS image sensor fragment at an initial stage of processing and in accordance with another embodiment of the invention;

FIGS. 8-10 illustrate the CMOS image sensor of FIG. 7 at intermediate steps of processing;

FIG. 11 is a diagrammatic side sectional view of a CMOS image sensor fragment resulting from the processes depicted in FIGS. 7-10;

FIGS. 12 and 13 illustrate the CMOS image sensor of FIG. 7 at intermediate steps of processing;

FIG. 14 is a diagrammatic side sectional view of a CMOS image sensor fragment resulting from the processes depicted in FIGS. 7-10 and 12-13;

FIG. 16 is diagrammatic side sectional view of a CMOS image sensor fragment at an initial stage of processing and in accordance with another embodiment of the invention;

FIGS. 17-19 are diagrammatic side sectional views of the CMOS image sensor of FIG. 16 at an intermediate stages of processing;

FIG. 20 is a diagrammatic side sectional view of a CMOS image sensor fragment resulting from the processes depicted in FIGS. 17-19; and

FIG. 21 is a schematic diagram of a processor system incorporating a CMOS image sensor constructed in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way, of illustration of specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

The terms “wafer” and “substrate” are to be understood as including silicon, silicon-on-insulator (SOI), or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, or gallium-arsenide.

The term “pixel” refers to a picture element unit cell containing a photosensor and transistors for converting electromagnetic radiation to an electrical signal. For purposes of illustration, a representative pixel is illustrated in the figures and description herein, and typically fabrication of all pixels in an image sensor will proceed simultaneously in a similar fashion.

Applicant proposes several trench isolation techniques to isolate areas of semiconductor devices and in an exemplary embodiment to minimize dark current and suppress leakage current in CMOS image sensors, as described below with reference to FIGS. 2-15. To better illustrate these techniques, a brief description of an exemplary CMOS image sensor pixel is described first with reference to FIGS. 1A and 1B hereinbelow. However, it should be noted that the invention is not limited to CMOS image sensors and may be used in any suitable device, for example, a DRAM, flash memory, SRAM, microprocessor, DSP or ASIC.

Referring now to FIGS. 1A and 1B, a semiconductor wafer fragment of an exemplary CMOS image sensor four-transistor (4T) pixel, generally designated by reference numeral 10, is shown. It should be noted that while FIGS. 1A-1B show the use of a transfer gate 50 and associated transistor, the transfer gate 50 provides advantages, but is not required. Thus, the invention may be used in any CMOS imager including, for example, a three transistor (3T) environment where the transfer gate is omitted and an n-type charge collection region of a photodiode is connected with an n-type diffusion region 21. The CMOS image sensor 10 generally comprises a charge collection region 21 for collecting charges generated by light incident on the pixel and transfer gate 50 for transferring photoelectric charges from the collection region 21 to a sensing node, typically a floating diffusion region 25. The floating diffusion region is electrically connected to the gate of an output source follower transistor. The pixel also includes a reset transistor 40 for resetting the sensing node to a predetermined voltage before sensing a signal, a source follower transistor 60 which receives at its gate an electrical signal from the sensing node 25, and a row select transistor 80 for outputting a signal from the source follower transistor 60 to an output terminal in response to an address signal.

The exemplary CMOS image sensor uses a pinned photodiode as the charge collection region 21. The pinned photodiode is termed such since the potential in the photodiode is pinned to a constant value when the photodiode is fully depleted. The pinned photodiode has a photosensitive or p-n-p junction region comprising a p-type surface layer 24 and an n-type photodiode region 26 within a p-type active layer 20. The pinned photodiode includes two p-type regions 20, 24 so that the n-type photodiode region is fully depleted at a pinning voltage. Impurity doped source/drain regions 22, preferably having n-type conductivity, are provided about the transistor gates 40, 60, 80. The floating diffusion region 25 adjacent to transfer gate 50 is also preferable n-type.

In a typical CMOS image sensor, trench isolation regions 28 formed in the active layer 20 are used to isolate the pixels. FIGS. 1A and 1B illustrate typical STI isolation trenches 28. The trench isolation regions 28 are formed using a typical STI process and are generally formed by etching a trench in the doped active layer or substrate 20 via a directional etching process, such as Reactive Ion Etching (RIE), or etching with a preferential anisotropic etchant used to etch into the doped active layer 20 to a sufficient depth, generally about 1000 Angstroms to 3000 Angstroms.

The trenches are then filled with an insulating material, for example, silicon dioxide, silicon nitride, ON (oxide-nitride), NO (nitride-oxide), or ONO (oxide-nitride-oxide).

The gate stacks for the pixel transistors are formed before or after the trench is etched. The order of these preliminary process steps may be varied as is required or convenient for a particular process flow, for example, if a known photogate sensor (not shown) which overlaps the transfer gate is desired, the gate stacks must be formed before the photogate, but if a non-overlapping photogate is desired, the gate stacks may be formed after photogate formation.

A translucent or transparent insulating layer 30 is formed over the CMOS image sensor. Conventional processing methods are then carried out to form, for example, contacts 32 (shown in FIG. 1A) in the insulating layer 30 to provide an electrical connection to the source/drain regions 22, the floating diffusion region 25, and other wiring to connect gate lines and other connections in the sensor 10. For example, the entire surface may then be covered with a passivation layer of e.g., silicon dioxide, BSG, PSG, or BPSG, which is planarized and etched to provide contact holes, which are then metallized to provide contacts to the photogate (if used), reset gate, and transfer gate.

In CMOS image sensors depicted in FIGS. 1A and 1B, electrons are generated by light incident externally and stored in the n-type photodiode region 26. These charges are transferred to the diffusion node 25 by the gate structure 50 of the transfer transistor. The source follower transistor produces an output signal from the transferred charges. A maximum output signal is proportional to the number of electrons extracted from the n-type photodiode region 26. The maximum output signal increases with increased electron capacitance or acceptability of the photodiode. The electron capacity of pinned photodiodes typically depends on doping levels and the dopants implanted to form regions 24, 26, 20.

A problem associated with the shallow trench isolation technique is photon diffusion under the shallow trench isolation structure from one pixel to an adjacent pixel. Attempts have been made to enhance isolation by implanting ions beneath the shallow trench isolation structure. However, these implants result in high current leakage. The invention provides a novel technique for improved isolation between adjacent pixels that does not require additional implants beneath the trench, thereby minimizing the generation of dark current in the CMOS image sensor.

Another consideration in CMOS image sensor fabrication are isolation design rules are constructed to make sure that there is enough margin to prevent punch-through in CMOS circuits. For example, the trench 28 separates the source/drain regions 22 of one pixel from the active layer of an adjacent pixel. Accordingly shallow trenches are generally sufficiently wide to allow a margin adequate enough to prevent punch-through or current leakage. The invention further provides novel techniques for preventing current leakage while allowing tighter design rules in CMOS circuits.

A first embodiment according to the invention is now described with reference to FIGS. 2-6. Applicant proposes an STI process, which uses an isolation trench filled with a doped conductive material containing silicon. Shallow trench isolation regions for CMOS image sensors generally have a depth of less than about 3000 Angstroms and generally around about 2000 to about 2500 Angstroms. Typically, shallow trench regions are filled with a conventional insulator, such as oxides or high density plasma (HDP) oxides. However, it is difficult to fill trenches having a depth greater than 2500 Angstroms with conventional insulators due to the limited spacing within the trench, for example, undesirable voids or air gaps are formed when oxides are used to fill trenches having a depth greater than about 2500 Angstroms. In accordance with the first embodiment of the invention, Applicant proposes filling trenches with conductive materials containing silicon, preferably polysilicon or silicon-germanium. Conductive materials containing silicon may be easily deposited into trenches of various depths, unlike conventional insulation materials, e.g., silicon dioxide, silicon nitride, NO, ON, HDP, and ONO, which are difficult to fill in deep trenches. Thus, using a conductive material containing silicon to fill the trench 328 will allow easy formation of a trench, particularly, a deep trench having a depth greater than about 2000 Angstroms, and preferably about 4000 Angstroms to about 5000 Angstroms.

Generally, the deeper the trench the better the isolation. With respect to CMOS image sensors in particular, the deeper the trench the higher the electron storage capacitance of the CMOS image sensor. A trench according to the invention is deeper than a shallow trench, and accordingly has longer sidewalls than a shallow trench. Therefore, the longer sidewalls allow for a larger electrical connection region 323 along the sidewalls of the trench such that electron storage capacitance, e.g., hole accumulation, in the electrical connection region 323 is increased in accordance with the invention.

In a CMOS image sensor having a trench filled with a conductive material containing silicon in accordance with the present invention, as shown in FIG. 2, a trench 328 is etched into a doped active layer 320. A resist and mask are applied, and photolithographic techniques are used to define the area to be etched-out. A directional etching process, such as Reactive Ion Etching (RIE), or etching with a preferential anisotropic etchant is used to etch into the doped active layer 320 to form the trench 328. The resist and mask are removed leaving a structure that appears as shown in FIG. 2.

Referring now to FIG. 3, an oxide, i.e., SiO₂ or other dielectric liner 327 is grown within the trench 328. The oxide liner may be formed of NO, ON, or ONO among many other suitable materials. The dielectric liner 327 may be substantially conformal. In other words, the thickness of the liner 327 is substantially the same along the sidewalls 319 and at the bottom of the trench 328. In general, the thickness of the dielectric liner 327 along the sidewalls should be at least about 100 Angstroms.

Referring now to FIG. 4, a highly doped (in-situ doped) n-type or p-type conductive material containing silicon 329 is deposited to fill the trench 328. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. Alternatively, as shown in FIG. 5, the trench 328 may be filled with a conductive material containing silicon 329 then, a masked ion implant (indicated by arrows) may be performed to dope the conductive material containing silicon. For example, in the case of a p-type active layer 320, with p-type wells, p-type ions such as boron (B) can be implanted into the conductive material containing silicon using a photoresist mask 326. Similarly, in the case of an n-type active layer 320 with n-type wells, n-type ions such as phosphorous (P), arsenic (As), or antimony (Sb) can be implanted.

Conductive materials containing silicon are easily filled into deep trenches. The deeper the trench, the harder it is to fill the trench with conventional insulators. Oxides and other conventional insulators form voids or air gaps when used to fill deep trenches. However, in accordance with the invention, a trench may be filled with a conductive material containing silicon easily and effectively.

An exemplary CMOS image sensor in accordance with the invention and having a pinned photodiode 321 is shown in FIG. 6. The pinned photodiode 321 has a p-type surface layer 324 and an n-type photodiode region 326 within a p-type active layer 320. A junction is formed around the entirety of the n-type region 326. An impurity doped floating diffusion region 325, preferably having n-type conductivity, is provided on one side of the channel region of transfer gate 350, the other side of which has a portion of n-type region 326. A trench isolation region 328 is formed in the active layer 320 adjacent to but spaced from the n-type region 321. An electrical connection region 323 for providing hole accumulation is formed adjacent the sidewalls of the trench isolation region 328. The trench isolation region 328 is formed as described above with respect to FIGS. 2-5.

The gate stacks, for example the transfer gate 350, may be formed before or after the trench is etched. The order of these process steps may be varied as is required or convenient for a particular process flow, for example, if a photogate sensor which overlaps the transfer gate is desired, the gate stacks must be formed before the photogate, but if a non-overlapping photogate is desired, the gate stacks may be formed after photogate formation.

A translucent or transparent insulating layer 330 is formed over the CMOS image sensor 300. Conventional processing methods are then carried out to form for example, contacts (not shown) in the insulating layer 330 to provide an electrical connection to the source/drain regions 322, the floating diffusion region 325, and other wiring to connect gate lines and other connections in the sensor 300. For example, the entire surface may then be covered with a passivation layer, of e.g., silicon dioxide, BSG, PSG, or BPSG, which is CMP planarized and etched to provide contact holes, which are then metallized to provide contacts to the photogate (if used), reset gate, and transfer gate.

The use of a trench in accordance with the invention provides improved isolation between pixels. The deeper trench better inhibits electrons from diffusing under the isolation trench to an adjacent pixel thereby preventing cross-talk between neighboring pixels. Accordingly, by enhancing isolation via a deeper trench, additional implants under the trench are not necessary, therefore by reducing the implants needed for isolation, current leakage is also reduced. Another advantage of the invention, is that the use of a deep trench filled with a conductive material containing silicon in accordance with the invention provides a deeper hole accumulation region, thereby increasing electron storage capacity. Also the deeper trench allows for tighter isolation design rules. Deeper trenches may also be narrower than shallow trenches, while still providing effective isolation between neighboring regions. Accordingly, the source/drain regions of one pixel may be brought closer to the active layer of an adjacent pixel, by narrowing the width of the deep trench.

A second embodiment in accordance with the invention is now described with reference to FIGS. 7-13. Referring now to FIG. 7, a trench 428 is etched into an active layer 420. The trench is preferably a deep trench having a depth greater than about 2500 Angstroms and preferably between about 4000 to about 5000 Angstroms. A resist and mask are applied, and photolithographic techniques are used to define the area to be etched-out. A directional etching process, such as RIE, or etching with a preferential anisotropic etchant is used to etch into the doped active layer 420 to form the trench 428. The resist and mask are removed leaving the FIG. 7 structure.

Referring now to FIG. 8, a nitride liner 432 is formed in the trench 428 via Chemical Vapor Deposition (CVD). This nitride liner 432 may be formed of any suitable nitride including NO, ON, ONO, and is preferably formed of silicon nitride.

Referring now to FIG. 9, an oxide, e.g. SiO₂ or other dielectric liner 427 is formed within the trench 428 and over the silicon nitride liner 432. The liner 427 may be non-conformal, in that its thickness may vary along the trench sidewalls 429. A relatively thick liner can be formed near the bottom of the trench and a thinner liner formed near the top of the trench. Non-conforming materials such as the well-known PSG, BPSG, SOG can be used to produce the liner 427.

Referring now to FIG. 10, a bottom portion of the oxide liner 427 and nitride liner 432 is stripped away. This can be accomplished by an anisotropic dry etch or a masked wet or dry etch.

Referring now to FIG. 11, a selective epitaxial layer 433 is grown to fill the trench 428 with silicon. The epitaxial layer 433 may be grown using any suitable technique and may be grown as a single layer or multi-layer. The epitaxial layer 443 is grown in directly on a surface of the active layer 420 to provide a direct electrical contact to the doped active layer 420 through the trench while providing improved field isolation between pixels. Providing a direct electrical contact to the active layer in accordance with the invention eliminates the need for a top contact, therefore saving space and allowing for tighter pixel formation.

Referring now to FIG. 12, in accordance with yet another embodiment of the invention, the selective epitaxial layer 433 is grown to partially fill the trench 428 with silicon.

Referring now to FIG. 13, a deposition process is performed to fill the rest of the trench with a filler material 434. The filler material is preferably an oxide material and is more preferably an HDP oxide. Alternatively, a conductive material containing silicon, for example polysilicon or silicon-germanium, may also be used to fill the rest of the trench 428.

By providing an epitaxial layer 433, the amount of oxide needed to fill the trench is reduced. Accordingly by using a reduced amount of oxide, or not using oxide in situations where conductive material containing silicon is used to fill the rest of the trench or when the trench is filled with the epitaxial layer 433 (as shown in FIG. 11), a deep trench in accordance with the invention may be formed. As discussed above deep trenches provide improved isolation and in the case of CMOS image sensors, prevention of cross-talk between adjacent pixels. And also as discussed above with regard to the first embodiment, the use of a deep trench to provide improved isolation eliminates the need to use excess implants beneath the trench, thereby reducing dark current in CMOS image sensors caused by current leakage. A selective-EPI filled or partially filled trench according to the invention may be used in combination with other aspects of the invention, for example, the selective-EPI-partially filled trench may be used along with a deep trench filled with a conductive material containing silicon.

An exemplary CMOS image sensor in accordance with the invention and having a pinned photodiode 421 is shown in FIG. 14. The pinned photodiode 421 has a p-type surface layer 424 and an n-type photodiode region 426 within a p-type active layer 420. A junction is formed around the entirety of the n-type region 426. An impurity doped floating diffusion region 425, preferably having n-type conductivity, is provided on one side of the channel region of transfer gate 450, the other side of which has a portion of n-type region 426. A trench isolation region 428 is formed in the active layer 420 adjacent to but spaced from n-type region 421. An electrical connection region 423 for providing hole accumulation is formed adjacent the sidewalls of the trench isolation region 428. The trench isolation region 428 is formed as described above with respect to FIGS. 7-13.

The gate stacks, for example transfer gate 450, may be formed before or after the trench is etched. The order of these preliminary process steps may be varied as is required or convenient for a particular process flow, for example, if a photogate sensor which overlaps the transfer gate is desired, the gate stacks must be formed before the photogate, but if a non-overlapping photogate is desired, the gate stacks may be formed after photogate formation.

A translucent or transparent insulating layer 430 is formed over the CMOS image sensor 400. Conventional processing methods are then carried out to form for example, contacts (not shown) in the insulating layer 430 to provide an electrical connection to the source/drain regions 422, the floating diffusion region 425, and other wiring to connect gate lines and other connections in the sensor 400. For example, the entire surface may then be covered with a passivation layer, of e.g., silicon dioxide, BSG, PSG, or BPSG, which is CMP planarized and etched to provide contact holes, which are then metallized to provide contacts to the photogate (if used), reset gate, and transfer gate.

Pixel arrays according to the invention, and described with reference to FIGS. 2-14, may be further processed as known in the art to arrive at CMOS image sensors having the functions and features of those discussed with reference to FIGS. 2-14.

A further exemplary embodiment in accordance with the invention is now described with reference to FIGS. 15-20. Referring now to FIG. 15, a first trench (opening) 528 is etched into a doped active layer 520. The first trench 528 is formed to a first depth D₁ and having a first width W₁. A directional etching process, such as RIE, or etching with a preferential anisotropic etchant is used to etch into the doped active layer 520 to form the trench 528.

Referring now to FIG. 16, an oxide, i.e., SiO₂ or other dielectric liner 527 is grown within the trench 528. The oxide liner may be formed of NO, ON, or ONO among many other suitable materials. The liner 527 may be substantially conformal. Desirably, the thickness of the dielectric liner 527 along the sidewalls of the first trench. 528 should be at least about 50 Angstroms (Å).

Optionally, an additional insulating liner, e.g., a nitride liner 532 is formed in the trench 528 via, e.g., Chemical Vapor Deposition (CVD). This nitride liner 532 may be formed of any suitable nitride including NO, ON, ONO, and preferably formed of silicon nitride.

A spacer material 540 is formed within the trench 528 and over the oxide layer 527 and optional silicon nitride layer 532. This spacer material 540 may be, e.g., a nitride, an oxide or polysilicon.

Referring now to FIG. 17, bottom portions of the spacer material 540, oxide liner 527 and nitride liner 532 are removed from a portion of a bottom surface 521 of the first trench 528. This can be accomplished by, e.g., an anisotropic dry etch or a masked wet or dry etch.

A second trench (opening) 548 is etched from the bottom surface 521 to a second depth D₂ in the active layer 520. The second trench is etched having a second width W₂, which is smaller than the width W₁ of the first trench. A directional etching process, such as RIE, or etching with a preferential anisotropic etchant is used to etch into the doped active layer 520 to form the second trench 548. Together, the first and second trenches 528, 548 have a combined depth of D₁+D₂. According to one exemplary embodiment, the depth D₁+D₂ is greater than about 1000 Angstroms. Desirably, the depth D₁+D₂ is greater than about 2000 Angstroms, and most desirably between about 4000 Angstroms to about 5000 Angstroms.

Referring to FIG. 18, a second oxide layer 529 is formed over the spacer material 540 along sidewalls of the first trench 528 and approximately fills the second trench 548. In one exemplary embodiment, the oxide layer 529 is a doped oxide layer, such as borosilicate glass (BSG) having a boron concentration within the range of about 1×10¹⁹ to 1×10²⁰ cm⁻³. After the doped oxide layer 529 is formed, subsequent processing steps utilizing heat cause the dopants to diffuse from the layer 529 into the trench sidewall and bottom regions 538. Optionally, sidewall regions 537 of the trench 528 and substrate 520 surface regions 539 adjacent the trench 528 can also be doped to a same conductivity type as the doped oxide layer 529. For example, when the doped oxide layer is a p-type layer, p-type dopants (e.g., boron or other p-type dopant) can be implanted into the regions 537 and 537.

A deposition process is performed to fill any remaining area of the trenches 528, 548 with a filler material 580. The filler material 580 is preferably a conductive material containing silicon, for example polysilicon or silicon-germanium, may also be used to fill the rest of the trenches 528, 548. The conductive material may be doped to a desired conductivity type, e.g., n-type or p-type. Alternatively, an insulting material can be used to fill the remainder of the trenches 528, 548, such as an oxide material, e.g., an HDP oxide or spun on dielectric (SOD) oxide. The resulting isolation structure 544 is shown in FIG. 19

An exemplary CMOS image sensor including the isolation structure 544 and having a pinned photodiode 521 is shown in FIG. 20. The pinned photodiode 521 has a p-type surface layer 524 and an n-type photodiode region 526 within a p-type active layer 520. A junction is formed around the entirety of the n-type region 526. An impurity doped floating diffusion region 525, preferably having n-type conductivity, is provided on one side of the channel region of transfer gate 550, the other side of which has a portion of n-type region 526. A trench isolation region 544 is formed in the active layer 520 adjacent to but spaced from n-type region 521. An electrical connection region 523 for providing hole accumulation is formed adjacent the sidewalls of the trench isolation region 544. The trench isolation region 544 is formed as described above with respect to FIGS. 15-19.

In the image sensor 500, providing doped region 538, and optionally regions 537, 539, providing doped regions 537, 538, 539 can provide better isolation between adjacent pixels and reduce cross-talk between pixels. Further, doped regions 537, 538, 539 can serve to ensure that the p-type surface layer 524 of the pinned photodiode 521 is pinned to the voltage applied to the substrate 520.

The gate stacks, for example transfer gate 550, may be formed before or after the trench is etched. The order of these preliminary process steps may be varied as is required or convenient for a particular process flow, for example, if a photogate sensor which overlaps the transfer gate is desired, the gate stacks must be formed before the photogate, but if a non-overlapping photogate is desired, the gate stacks may be formed after photogate formation.

A translucent or transparent insulating layer 530 is formed over the CMOS image sensor 500. Conventional processing methods are then carried out to form for example, contacts (not shown) in the insulating layer 530 to provide an electrical connection to the source/drain regions 522, the floating diffusion region 525, and other wiring to connect gate lines and other connections in the sensor 500. For example, the entire surface may then be covered with a passivation layer, of e.g., silicon dioxide, BSG, PSG, or BPSG, which is CMP planarized and etched to provide contact holes, which are then metallized to provide contacts to the photogate (if used), reset gate, and transfer gate.

Pixel arrays according to the invention, and described with reference to FIGS. 2-14, may be further processed as known in the art to arrive at CMOS image sensors having the functions and features of those discussed with reference to FIGS. 2-14.

A typical processor based system, which includes a CMOS image sensor according to the invention is illustrated generally at 642 in FIG. 21. A processor based system is exemplary of a system having digital circuits, which could include CMOS image sensors. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision, vehicle navigation, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system and data compression system for high-definition television, all of which can utilize the present invention.

A processor based system, such as a computer system, for example generally comprises a central processing unit (CPU) 644, for example, a microprocessor, which communicates with an input/output (I/O) device 646 over a bus 652. The CMOS image sensor 642 also communicates with the system over bus 652. The computer system 600 also includes random access memory (RAM) 648, and, in the case of a computer system may include peripheral devices such as a flash memory card 654, or a compact disk (CD) ROM drive 656 which also communicate with CPU 644 over the bus 652. It may also be desirable to integrate the processor 654, CMOS image sensor 642 and memory 648 on a single IC chip.

The above description and drawings are only to be considered illustrative of exemplary embodiments, which achieve the features and advantages of the invention. Modification and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims. 

1. A structure for isolating areas in an image sensor, said structure comprising: a trench formed in an image sensor substrate between adjacent pixels, said trench comprising first and second portions, said first portion having a first width, said second portion having a second width and being below said first portion, said first width being greater than said second width; a first insulating liner formed along at least lateral sidewalls of said first portion; a spacer material formed along at least lateral sidewalls of said insulating liner and filling said second portion; and a filler material over said spacer material and within said first portion.
 2. The structure of claim 1, wherein said first insulating liner comprises an oxide material.
 3. The structure of claim 1, wherein said insulating liner is non-conformal.
 4. The structure of claim 1, wherein said spacer material comprises an oxide material.
 5. The structure of claim 1, wherein said spacer material comprises a doped oxide material.
 6. The structure of claim 1, wherein said spacer material comprises a nitride material.
 7. The structure of claim 1, wherein said spacer material comprises polysilicon.
 8. The structure of claim 1, further comprising a nitride liner between said first insulating liner and said spacer material.
 9. The structure of claim 1, wherein said filler material is a conductive material.
 10. The structure of claim 9, wherein said conductive material comprises silicon.
 11. The structure of claim 9, wherein said filler material comprises polysilicon.
 12. The structure of claim 9, wherein said filler material comprises silicon-germanium.
 13. The structure of claim 7, wherein said filler material is an insulating material.
 14. The structure of claim 13, wherein said filler material comprises an oxide material.
 15. A structure for isolating areas in a semiconductor device, said structure comprising: a trench formed in a substrate, said trench comprising first and second portions, said first portion having a first width, said second portion having a second width and being below said first portion, said first width being greater than said second width; a first insulating liner formed along at least lateral sidewalls of said first portion; a spacer material formed along at least lateral sidewalls of said insulating liner and filling said second portion; and a filler material deposited over said spacer material and within said first portion.
 16. The structure of claim 15, wherein said first insulating liner comprises an oxide material.
 17. The structure of claim 15, wherein said insulating liner is non-conformal.
 18. The structure of claim 15, wherein said spacer material comprises an oxide material.
 19. The structure of claim 15, wherein said spacer material comprises a doped oxide material.
 20. The structure of claim 15, wherein said spacer material comprises a nitride material.
 21. The structure of claim 15, wherein said spacer material comprises polysilicon.
 22. The structure of claim 15, further comprising a nitride liner between said first insulating liner and said spacer material.
 23. The structure of claim 15, wherein said filler material comprises a conductive material.
 24. The structure of claim 23, wherein said conductive material comprises silicon.
 25. The structure of claim 23, wherein said conductive material comprises polysilicon.
 26. The structure of claim 23, wherein said conductive material comprises silicon-germanium.
 27. The structure of claim 21, wherein said filler material comprises an insulating material.
 28. The structure of claim 27, wherein said filler material comprises an oxide material.
 29. The structure of claim 15, wherein said semiconductor device comprises a CMOS image sensor.
 30. A method of forming a structure for isolating areas in a semiconductor device, said method comprising the steps of: forming a first opening to a first depth in an active area of a semiconductor substrate; depositing a first insulating lining in said first opening; depositing a spacer material over said first insulating lining; removing a portion of the spacer material and first insulating material at a bottom of said first opening; forming a second opening to a second depth within said first opening; forming a second insulating liner over said spacer material and approximately filling said second opening; and forming a filler material within said first opening and over said second insulating liner.
 31. The method of claim 30, wherein the act of forming said first insulating liner comprises forming an oxide material.
 32. The structure of claim 30, wherein the act of forming said first insulating liner comprises forming a non-conformal liner.
 33. The method of claim 30, wherein the act of forming said spacer material comprises forming an oxide material.
 34. The method of claim 30, wherein the act of forming said spacer material comprises forming a doped oxide material.
 35. The method of claim 30, wherein the act of forming said spacer material comprises forming a nitride material.
 36. The structure of claim 30, wherein the act of forming said spacer material comprises forming polysilicon.
 37. The method of claim 30, further comprising forming a nitride liner between said first insulating liner and said spacer material.
 38. The method of claim 30, wherein the act of forming said filler material comprises forming a conductive material.
 39. The method of claim 38, further comprising doping the conductive material to a conductivity type.
 40. The method of claim 38, wherein the act of forming said filler material comprises forming silicon.
 41. The method of claim 38, wherein the act of forming said filler material comprises forming polysilicon.
 42. The method of claim 38, wherein the act of forming said filler material comprises forming silicon-germanium.
 43. The method of claim 36, wherein the act of forming said filler material comprises forming an insulating material.
 44. The method of claim 43, wherein the act of forming said filler material comprises forming an oxide material.
 45. The method of claim 30, wherein said act of forming said first opening comprises forming said first opening in a CMOS image sensor substrate.
 46. The method of claim 30, wherein said acts of forming said first and second openings comprise forming said first and second openings such that together said first and second depths are between about 1000 Angstroms to about 5000 Angstroms.
 47. The method of claim 30, wherein said acts of forming said first and second openings comprise forming said first and second openings such that together said first and second depths are greater than about 2000 Angstroms. 